📚 AITL Silicon Pathway — Documentation Index
Welcome to the official documentation site for AITL Silicon Pathway.
This page serves as the root index for all chapters, diagrams, and reference materials.
🔗 Official Links
| Language | GitHub Pages 🌐 | GitHub 💻 |
|---|---|---|
| 🇺🇸 English |  |
 |
⚠ Diagram Rendering Notice
The system pathway diagram above is written in Mermaid.
Due to current limitations of GitHub Pages, Mermaid diagrams are not rendered on this site.Please refer to the GitHub repository view (linked above) to see the diagram correctly rendered.
🧭 Full System Pathway
flowchart TD
PY[Python Baseline Model]
SPEC[FSM Specification]
RTL[Verilog RTL]
OL[OpenLane Flow]
GDS[GDSII Layout]
EXT[RC Extraction]
SPICE[SPICE Simulation]
PY --> SPEC
SPEC --> RTL
RTL --> OL
OL --> GDS
GDS --> EXT
EXT --> SPICE
The project explores the complete engineering pipeline:
Python → Verilog (RTL) → OpenLane → GDSII → Magic RC Extraction → SPICE Simulation
📘 Chapter Index
| Chapter | GitHub Pages | GitHub Source | Description |
|---|---|---|---|
| Chapter 1 | docs/chapter1 | /chapter1_python_model | Python baseline FSM model (PID × FSM × LLM reference) |
| Chapter 2 | docs/chapter2 | none | Formal FSM specification and Verilog RTL design |
| Chapter 3 | docs/chapter3 | none | RTL simulation and ASIC-flow feasibility check (OpenLane concept level) |
| Chapter 4 | docs/chapter4 | none | Formal and structural correctness of FSM (invariants, safety, equivalence) |
| Chapter 5 | docs/chapter5 | none | Executable verification of FSM correctness (assertions, simulation, equivalence checks) |
🧩 AITL Architecture Overview
flowchart TD
R[Reference]
E[Error]
PID[PID Controller]
FSM[FSM Supervisor]
PLANT[Plant]
Y[Output]
LLM[LLM Meta Control]
R --> E
Y --> E
E --> PID
PID --> PLANT
PLANT --> Y
FSM --> PID
FSM --> PLANT
LLM -. tuning .-> PID
LLM -. policy .-> FSM
The AITL architecture consists of:
- PID Layer — Numerical real-time control
- FSM Layer — Supervisory logic (canonical model for RTL)
- LLM Layer — Adaptive meta-controller
📄 Detailed Documentation Structure
docs/
├─ index.md
├─ chapter1/
│ ├─ index.md
│ ├─ overview.md
│ ├─ python_model.md
│ ├─ fsm.md
│ ├─ api.md
│ ├─ getting_started.md
│ └─ images/
│ ├─ aitl_3layer.png
│ ├─ fsm_state_diagram.png
│ ├─ controller_data_flow.png
│ └─ step_response_timeline.png
├─ chapter2/
├─ chapter3/
├─ chapter4/
├─ chapter5/
└─ README.md
🔗 Quick Navigation
- 👉 Chapter 1 — Python Baseline FSM
- 👉 Chapter 2 — FSM Specification & Verilog RTL
- 👉 Chapter 3 — Simulation & ASIC Flow Feasibility
- 👉 Chapter 4 — FSM Formal Correctness (Invariants & Safety)
- 👉 Chapter 5 — Executable Verification & Equivalence Checking
👤 Author
| 📌 Item | Details |
|---|---|
| Name | Shinichi Samizo |
| Expertise | Semiconductor devices (logic, memory, high-voltage mixed-signal) Thin-film piezo actuators for inkjet systems Printhead productization, BOM management, ISO training |
| GitHub |  |
📄 License
| 📌 Item | License | Description |
|---|---|---|
| Source Code | MIT License | Free to use, modify, and redistribute |
| Text Materials | CC BY 4.0 or CC BY-SA 4.0 | Attribution required; share-alike applies for BY-SA |
| Figures & Diagrams | CC BY-NC 4.0 | Non-commercial use only |
| External References | Follow the original license | Cite the original source properly |
💬 Feedback
Feedback, ideas, and discussions are welcome.
