🧩 Chapter 1 — Python Baseline Model

AITL Architecture: PID × FSM × LLM

This chapter introduces the foundational Python model of the AITL control architecture.
It also links to all detailed documentation pages of Chapter 1.

🔗 Official Links

Language	GitHub Pages 🌐	GitHub 💻
🇺🇸 English

⚠ Diagram Rendering Notice

The system pathway diagram above is written in Mermaid.
Due to current limitations of GitHub Pages, Mermaid diagrams are not rendered on this site.

Please refer to the GitHub repository view (linked above) to see the diagram correctly rendered.

📂 Documentation Index

🎯 Objectives of Chapter 1

• Understand the three-layer AITL architecture
• Implement the Python baseline model
• Learn the canonical FSM rules (later used for RTL)
• Run simulations:
  • Step response
  • Fault scenario
• Establish the behavioral golden model for hardware translation

🧭 FSM Overview

flowchart TD
    PY[Python Baseline Model]
    SPEC[FSM Specification]
    RTL[Verilog RTL]
    OL[OpenLane Flow]
    GDS[GDSII Layout]
    EXT[RC Extraction]
    SPICE[SPICE Simulation]

    PY --> SPEC
    SPEC --> RTL
    RTL --> OL
    OL --> GDS
    GDS --> EXT
    EXT --> SPICE

🔧 Controller Data Flow

flowchart TD
    R[Reference]
    E[Error]
    PID[PID Controller]
    FSM[FSM Supervisor]
    PLANT[Plant]
    Y[Output]
    LLM[LLM Meta Control]

    R --> E
    Y --> E
    E --> PID
    PID --> PLANT
    PLANT --> Y

    FSM --> PID
    FSM --> PLANT

    LLM -. tuning .-> PID
    LLM -. policy .-> FSM

📈 Step Response Simulation

⚠ Fault Scenario Simulation

🚀 Next Steps

Continue to:

👉 overview.md
or
👉 python_model.md

© AITL Silicon Pathway Project