Chapter2: FSM → Verilog RTL

AITL Silicon Pathway

This chapter formalizes the Finite State Machine (FSM) defined in Chapter1
and translates it from a Python-level specification into synthesizable Verilog RTL.

The goal is not only to write RTL code, but to establish a reproducible and deterministic mapping process from software FSM models to hardware implementations suitable for ASIC synthesis using OpenLane.

🔗 Official Links

Language	GitHub Pages 🌐	GitHub 💻
🇺🇸 English

🎯 Objectives

• Convert a Python-based FSM into a formal hardware specification
• Fully hardware-implement the FSM layer in the PID × FSM × LLM architecture
• Define clear and reusable rules for translating FSM behavior into Verilog RTL
• Avoid ad-hoc RTL coding by fixing state, transition, and output semantics

🧠 Role of FSM in AITL

LLM (Outer Layer)
  └─ Anomaly detection, redesign, parameter updates

FSM (Middle Layer)  ← Focus of this chapter
  └─ Mode management, state transitions, control policy switching

PID (Inner Layer)
  └─ Real-time control (V–I response stabilization)

The FSM covered in this chapter has the following characteristics:

• Accepts decisions or flags generated by the LLM layer as input conditions
• Controls PID operation modes through explicit state transitions
• Is fully deterministic and synthesizable
• Is clearly separated from the real-time PID control loop

📂 Directory Structure

docs/chapter2/
├── README.md          ← Entry point of Chapter2
├── overview.md        ← Chapter overview and design flow
├── fsm_spec.md        ← Formal FSM specification
├── mapping_rules.md   ← Python-to-Verilog mapping rules
├── verilog_rtl.md     ← FSM RTL (skeleton → complete)
├── rtl_guidelines.md  ← ASIC / OpenLane RTL guidelines
└── assets/
    ├── fsm_diagram.mmd
    ├── state_table.csv
    ├── transition_table.csv
    └── signal_list.csv

📖 Recommended Reading Order

1. overview.md
   Understand the purpose and overall flow of Chapter2

2. fsm_spec.md
   Formalize the FSM using state tables, transition tables, and signal definitions

3. mapping_rules.md
   Learn how Python FSM constructs are mapped to Verilog RTL

4. verilog_rtl.md
   Examine the FSM RTL, from skeleton structure to a complete implementation

5. rtl_guidelines.md
   Learn ASIC-oriented RTL coding rules to avoid synthesis pitfalls

⚠ Out of Scope

The following topics are intentionally excluded from this chapter:

• OpenLane execution procedures
• Testbench implementation
• Lint or synthesis error handling
• VSCode or editor usage
• SoC integration and top-level wiring

These topics will be covered in Chapter3 and later.

🧩 Relationship to Other Chapters

• Chapter1
  FSM design at the Python level
  └ Conceptual behavior and control logic

• Chapter2 (this chapter)
  Formal specification and RTL realization of the FSM
  └ Hardware-level definition of states and transitions

• Chapter3 (planned)
  RTL simulation, synthesis, and ASIC flow
  └ Verification using OpenLane

✍️ Target Audience

• Engineers who want to translate FSM logic into RTL systematically
• Designers moving from Python-based models to ASIC implementation
• Readers interested in OpenLane-compatible FSM design
• Anyone studying the FSM layer of the AITL architecture

🔗 Related Chapters

• Chapter1: FSM Design (Python)
• Chapter3: RTL Simulation & ASIC Flow (planned)