🎓 Edusemi-v4x | Foundational Educational Materials for Semiconductor Product Development
🆕 Check the latest updates in the ChangeLog.
Review all recent modifications in the ChangeLog.
🔗 Official Links
| Language | GitHub Pages 🌐 | GitHub 💻 |
|---|---|---|
| 🇺🇸 English |  |
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| 🇯🇵 Japanese |  |
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📑 Table of Contents
- ✍️ Introduction
- 📘 Project Overview
- 🧭 Fundamentals
- 🧩 Applications
- 🛠 Practice
- 📦 Special Topics
- 🔗 Related Projects
- 👤 Author
- 📄 License
- 💬 Feedback
✍️ Introduction
Semiconductor technology began with the invention of the transistor and rapidly evolved with the advent of the MOS structure.
Miniaturization and integration have progressed in line with Moore’s Law, and LSIs have penetrated all fields.
However, fundamental areas such as physics, circuits, processes, and testing are often fragmented in educational contexts.
In practice, these are closely connected—circuits depend on device physics, and design is supported by process technology and reliability.
Edusemi focuses on the structural connections between fundamental technologies, fostering structural understanding with an eye toward applications.
💡 Design follows physics, and productization follows verification.
Visualizing the connection from physics → circuits → implementation → verification.
📘 Project Overview
Edusemi-v4x is an open educational resource covering the full range from design to manufacturing, testing, and quality assurance.
- 🎯 Target Audience: Engineering students, junior engineers, educators
- ⭐ Features: Emphasis on fundamental interconnections, coverage from design to mass production testing
- 🧪 Practice: sky130, OpenLane, Python, GitHub, ChatGPT integration
🧭 Fundamentals
Covers semiconductor physics, logic design, and process fundamentals essential for all applications.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
🧭 Chapter 1  |
Fundamentals of Semiconductor Physics and MOS Structure | Learn the semiconductor physics underlying MOS transistors and CMOS circuit design, from band structure to CMOS inverters, step by step. |
| 🧭 Chapter 2 |
Digital Logic and Logic Circuit Design | Covers the fundamentals of CMOS logic circuit design, from basic logic gates to complex logic, multiplexers, adders, and FSM design. |
| 🧭 Chapter 3 |
Process Evolution and Design Limits in CMOS | Learn the evolution of CMOS technology from 0.5µm to 90nm and the impact of physical limits on circuit design. |
| 🧭 Chapter 4 |
MOS Transistor Characteristics and Design Infrastructure | Organize the physics, dimensions, design rules, and PDK structure of MOSFETs to understand their operation, reliability, and limits from a designer’s perspective. |
| 🧭 Chapter 5a |
Spec Definition & Interface Design | Covers upstream design, module selection, and PoC integration. |
| 🧭 Chapter 5 |
SoC Design Flows and EDA Tools | Learn the full SoC development flow, the connection points between standard cell and physical design, and the basics of STA and DFT verification. |
| 🧭 Chapter 6 |
Test, Packaging, and Productization | Understand mass production processes (inspection, monitoring, reliability checks, shipment decisions) to prevent defective products from reaching the market. |
| 🧭 Chapter 7 |
Design Review and Cross-Functional Collaboration | Gain a systematic understanding of the purpose, structure, and cross-functional collaboration mechanisms of Design Reviews in semiconductor product development. |
🧩 Applications
Delves into applied semiconductor technologies and specialized design fields to develop practical design skills.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🧩 Chapter 1 |
Memory Technologies – Structure and Selection Guidelines | Understand the structure and operation of SRAM, DRAM, FeRAM, MRAM, and NAND; learn to compare them based on speed, non-volatility, endurance, area efficiency, and power consumption; and master integration, selection, and connection methods in SoC design. |
| 🧩 Chapter 2 |
High Voltage Devices | Learn the structure and layout design techniques of HV-CMOS and LDMOS devices, and understand their applications in power control, sensor interfaces, and high-voltage driver circuits. |
| 🧩 Chapter 3 |
ESD Protection Design | Understand ESD reliability risks in semiconductor ICs, and systematically learn protection device structures, layout strategies, test standards, and failure analysis. |
| 🧩 Chapter 4 |
Layout Design and Optimization | Learn methods for optimizing placement, routing, and geometric structures in IC layouts to ensure performance, reliability, and manufacturability. |
| 🧩 Chapter 5 |
Analog / Mixed-Signal Design | Understand the overall scope of AMS design, from basic circuits such as op-amps and comparators to layout design, noise countermeasures, and integration challenges with ADC/DAC. |
| 🧩 Chapter 5a |
0.18µm AMS Design Techniques | Learn countermeasures for variability, noise, and parasitics in 0.18µm AMS circuit design, and acquire techniques adaptable to a wide range of supply voltages and frequency bands. |
| 🧩 Chapter 5b |
Differentiated Analog Modules via Manufacturing Technology — Realizing 50% Reduction in 1/f Noise | Learn design and manufacturing strategies to leverage fabrication processes for reducing 1/f noise by over 50% and achieving low-noise MOS devices. |
| 🧩 Chapter 6 |
PDK and EDA Environment | Understand the components of a PDK, its integration with EDA tools, design rule checking, process compatibility, and the relationship with BSIM models. |
| 🧩 Chapter 7 |
Automation and Implementation Verification | Learn automation techniques from RTL design to physical layout verification, and master CI/CD verification flows alongside Lint, DRC, LVS, and STA. |
| 🧩 Chapter 8 |
FSM Design (Finite State Machine) | Understand the structure and operation of Moore and Mealy FSMs, and learn three-stage description methods in Verilog with state diagrams. |
| 🧩 Chapter 9 |
PLL and Clock Design | Learn PLL principles, skew/jitter countermeasures, and clock tree design to acquire high-precision clock generation and distribution techniques. |
🛠 Practice
Hands-on exercises with Python automation, Sky130 experiments, and OpenLane design to solidify skills.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🛠 Chapter 1 |
Python-Based Automation Tools for Semiconductor Design | Develop Python scripts to automate SPICE simulations, reliability model evaluations, and report analysis in conjunction with the Sky130 PDK and OpenLane flow. |
| 🛠 Chapter 2 |
Sky130 Experiments and SPICE-Based Characterization | Use the SkyWater Sky130 PDK to evaluate MOS characteristics (Vg–Id curves, Vth extraction) and predict BTI/TDBB, performing SPICE-based design verification. |
| 🛠 Chapter 3 |
Digital Design Practice Using OpenLane | Experience the LSI design flow from Verilog RTL to GDS generation, understanding the objectives and tools for synthesis, placement, routing, and DRC. |
| 🛠 Chapter 4 |
PoC Specifications and Design Implementation | Using minimal PoC circuits (FSM/MUX/Adder) with the Sky130 PDK, experience the process from specification creation to RTL design and physical implementation. |
| 🛠 Chapter 5 |
Evaluation and Reporting of Design Results | Evaluate implemented PoC circuits by analyzing simulation results, area/timing metrics, DRC/LVS checks, and propose improvements as part of the design feedback cycle. |
| 🛠 Chapter 6 |
SPICE Practice for Devices and Circuits | Reinforce concepts of FinFET, GAA, CFET, and WBG devices (SiC/GaN) by reproducing their behaviors in SPICE simulations, including Id–Vds, inverter VTC, and switching comparisons. |
📦 Special Topics
Focuses on cutting-edge topics such as advanced nodes, chiplets, and integrated control SoCs.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 📦 Chapter 1 |
Advanced Node Technologies – FinFET, GAA & CFET | Comprehensively explains the physical and electrical characteristics and design impacts of FinFET, GAA, and CFET structures, introducing advanced CMOS technologies beyond planar MOS limits. |
| 📦 Chapter 2 |
Chiplets and Advanced Packaging | Covers 2.5D/3D integration, TSV, and heterogeneous integration for chiplet architecture design, implementation, and reliability, enabling flexible design and scalability. |
| 📦 Chapter 2a |
Design Handling of Thermal, Stress, and Noise Constraints in SystemDK | Explains the concept of SystemDK and methods for addressing physical constraints such as SI/PI, thermal, stress, and EMI/EMC in design. |
| 📦 Chapter 3 |
SoC Implementation of Integrated Control System with FSM × PID × LLM | Based on the AITL-H three-layer control architecture, learn methods for functional separation, hierarchical collaboration, and SoC integration. |
| 📦 Chapter 4 |
RTL-to-GDSII Implementation of FSM×PID×LLM Control System with OpenLane | Using the Sky130 PDK, implement placement and routing (RTL-to-GDSII) for FSM, PID, and integrated SoC modules. |
| 📦 Chapter 5 |
Physical Verification and DFM Design Guidelines with PDK | Perform layout verification with the Sky130 PDK and acquire DFM design guidelines considering manufacturability. |
| 📦 Chapter 6 |
Research Paper: SystemDK with AITL | Proposes embedding PID+FSM+LLM control loops into EDA flows to compensate runtime RC delay, thermal coupling, and EMI variations, demonstrating guardband reduction and improved reliability across sub-2nm nodes. |
🔗 Related Projects
Sister projects linked with Edusemi, covering control theory, socio-industrial structures, and advanced technologies.
| 🌐 Project | Overview | Key Features |
|---|---|---|
| ➕ Edusemi-Plus |
Applied learning materials analyzing geopolitics, product strategy, AI, quantum, and investment. | - In-depth analysis of Apple Silicon, CHIPS Act, and Cryo-CMOS - Explores not only technology but also its societal context and background |
| 🎛️ EduController |
Covers control theory (PID, state-space) to AI control (NN, RL, LLM). | - Linked with PoC design and OpenLane control implementation - Design exercises in Python, RTL verification, FSM generation support |
| 🤖 AITL-H |
Three-layer control architecture: FSM (instinct) + PID (reason) + LLM (intelligence). | - PoC implementation for humanoid robot integrated control - Structurally linked with Edusemi Special Edition Chapters 3 & 4 |
👤 Author
Author with professional background in semiconductors and inkjet actuators, creating materials integrating theory and practice.
| 📌 Item | Details |
|---|---|
| Name | Shinichi Samizo |
| Education | M.Eng., Electrical and Electronic Engineering, Shinshu University |
| Career | Former engineer at Seiko Epson Corporation (1997–) |
| Expertise | Semiconductor devices (logic, memory, high-voltage mixed) Thin-film piezoelectric actuators for inkjet PrecisionCore printhead productization, BOM management, ISO training |
| ✉️ Email |  |
| 🐦 X |  |
| 💻 GitHub |  |
📄 License
Adopts a hybrid licensing model according to the nature of the materials, code, and diagrams.
Hybrid licensing based on the nature of the materials, code, and diagrams.
| 📌 Item | License | Description |
|---|---|---|
| Code | MIT License | Free to use, modify, and redistribute |
| Text materials | CC BY 4.0 or CC BY-SA 4.0 | Attribution required, share-alike for BY-SA |
| Figures & diagrams | CC BY-NC 4.0 | Non-commercial use only |
| External references | Follow the original license | Cite the original source |
💬 Feedback
Propose improvements or start discussions via GitHub Discussions.
