🎓 Edusemi-v4x | Foundational Educational Materials for Semiconductor Product Development
🔗 Official Links
| Language | GitHub Pages 🌐 | GitHub 💻 |
|---|---|---|
| 🇺🇸 English |  |
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| 🇯🇵 Japanese |  |
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📑 Table of Contents
- ✍️ Introduction
- 📘 Project Overview
- 🧭 Fundamentals
- 🧩 Applications
- 🛠 Practice
- 📦 Special Topics
- 🔗 Related Projects
- 👤 Author
- 📄 License
- 💬 Feedback
✍️ Introduction
Semiconductor technology began with the invention of the transistor and rapidly evolved with the advent of the MOS structure.
Miniaturization and integration have progressed in line with Moore’s Law, and LSIs have penetrated all fields.
However, fundamental areas such as physics, circuits, processes, and testing are often fragmented in educational contexts.
In practice, these are closely connected—circuits depend on device physics, and design is supported by process technology and reliability.
Edusemi focuses on the structural connections between fundamental technologies, fostering structural understanding with an eye toward applications.
💡 Design follows physics, and productization follows verification.
Visualizing the connection from physics → circuits → implementation → verification.
📘 Project Overview
Edusemi-v4x is an open educational resource covering the full range from design to manufacturing, testing, and quality assurance.
- 🎯 Target Audience: Engineering students, junior engineers, educators
- ⭐ Features: Emphasis on fundamental interconnections, coverage from design to mass production testing
- 🧪 Practice: sky130, OpenLane, Python, GitHub, ChatGPT integration
🧭 Fundamentals
Covers semiconductor physics, logic design, and process fundamentals essential for all applications.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
🧭 Chapter 1  |
Fundamentals of Semiconductor Physics and MOS Structure | Semiconductor physics underlying MOS transistors and CMOS design, from band structure to CMOS inverters, explained step by step. |
| 🧭 Chapter 2 |
Digital Logic and Logic Circuit Design | CMOS logic fundamentals, covering basic gates, complex logic, multiplexers, adders, and FSM design. |
| 🧭 Chapter 3 |
Process Evolution and Design Limits in CMOS | CMOS technology scaling from 0.5µm to 90nm and the impact of physical limits on circuit design. |
| 🧭 Chapter 4 |
MOS Transistor Characteristics and Design Infrastructure | MOSFET physics, dimensions, design rules, and PDK structure to understand operation, reliability, and design limits from a designer’s perspective. |
| 🧭 Chapter 5a |
Spec Definition & Interface Design | Upstream design, specification definition, module selection, and PoC integration. |
| 🧭 Chapter 5 |
SoC Design Flows and EDA Tools | End-to-end SoC development flow, including standard cell design, physical design interfaces, STA, and DFT basics. |
| 🧭 Chapter 6 |
Test, Packaging, and Productization | Mass production processes including inspection, monitoring, reliability checks, and shipment decisions to prevent defective products from reaching the market. |
| 🧭 Chapter 7 |
Design Review and Cross-Functional Collaboration | Design Review (DR) structure and purpose and cross-functional collaboration mechanisms in semiconductor product development. |
🧩 Applications
Delves into applied semiconductor technologies and specialized design fields to develop practical design skills.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🧩 Chapter 1 |
Memory Technologies – Structure and Selection Guidelines | SRAM, DRAM, FeRAM, MRAM, and NAND architectures, compared by speed, non-volatility, endurance, area efficiency, and power consumption, with a focus on SoC integration, selection, and interconnection. |
| 🧩 Chapter 2 |
High Voltage Devices | HV-CMOS and LDMOS structures and layout techniques, and their applications in power control, sensor interfaces, and high-voltage driver circuits. |
| 🧩 Chapter 3 |
ESD Protection Design | ESD reliability risks, covering protection device structures, layout strategies, test standards, and failure analysis for semiconductor ICs. |
| 🧩 Chapter 4 |
Layout Design and Optimization | Placement, routing, and geometric optimization techniques to ensure performance, reliability, and manufacturability (DFM). |
| 🧩 Chapter 5 |
Analog / Mixed-Signal Design | AMS design fundamentals, from op-amps and comparators to layout techniques, noise mitigation, and ADC/DAC integration challenges. |
| 🧩 Chapter 5a |
0.18µm AMS Design Techniques | Variability, noise, and parasitic countermeasures for 0.18µm AMS circuits, enabling operation across wide supply voltages and frequency ranges. |
| 🧩 Chapter 5b |
Differentiated Analog Modules via Manufacturing Technology — Realizing 50% Reduction in 1/f Noise | Manufacturing-aware design strategies achieving over 50% reduction in 1/f noise, enabling low-noise MOS device realization. |
| 🧩 Chapter 6 |
PDK and EDA Environment | PDK components, EDA tool integration, DRC, process compatibility, and BSIM models, forming the foundation of robust design environments. |
| 🧩 Chapter 7 |
Automation and Implementation Verification | Automation from RTL to physical verification, including Lint, DRC, LVS, STA, and CI/CD-based verification flows. |
| 🧩 Chapter 8 |
FSM Design (Finite State Machine) | Moore and Mealy FSM structures, with state diagrams and three-stage Verilog descriptions for control logic design. |
| 🧩 Chapter 9 |
PLL and Clock Design | PLL fundamentals, covering skew/jitter mitigation and clock tree design for high-precision clock generation and distribution. |
🛠 Practice
Hands-on exercises with Python automation, Sky130 experiments, and OpenLane design to solidify skills.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🛠 Chapter 0 |
Environment Setup and Toolchain Preparation | Complete toolchain setup for Chapters 1–3, including Python, VS Code, Git, ngspice, Sky130 PDK (volare), Magic, Netgen, KLayout, Docker, and WSL2, ensuring a fully functional environment for SPICE experiments, OpenLane design, and Python automation workflows. |
| 🛠 Chapter 1 |
Python-Based Automation Tools for Semiconductor Design | Python automation scripts for SPICE simulations, reliability model evaluation, and report analysis, integrated with the Sky130 PDK and OpenLane flow. |
| 🛠 Chapter 2 |
Sky130 Experiments and SPICE-Based Characterization | MOS characterization (Vg–Id curves, Vth extraction) and BTI/TDBB prediction using the SkyWater Sky130 PDK, enabling SPICE-based design verification. |
| 🛠 Chapter 3 |
Digital Design Practice Using OpenLane | End-to-end LSI design flow, from Verilog RTL to GDS generation, covering synthesis, placement, routing, and DRC with OpenLane. |
📦 Special Topics
Focuses on cutting-edge topics such as advanced nodes, chiplets, and integrated control SoCs.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 📦 Chapter 1 |
Advanced Node Technologies – FinFET, GAA & CFET | Physical and electrical characteristics and design impacts of FinFET, GAA, and CFET, introducing advanced CMOS technologies beyond planar MOS limits. |
| 📦 Chapter 2 |
Chiplets and Advanced Packaging | 2.5D/3D integration, TSV, and heterogeneous integration for chiplet architecture design, implementation, and reliability, enabling flexible design and scalability. |
| 📦 Chapter 2a |
Design Handling of Thermal, Stress, and Noise Constraints in SystemDK | SystemDK concepts and design methodologies for handling SI/PI, thermal, stress, and EMI/EMC constraints at the SoC–system integration level. |
🔗 Related Projects
Sister projects linked with Edusemi, covering control theory, socio-industrial structures, and advanced technologies.
| 🌐 Project | Overview | Key Features |
|---|---|---|
| ➕ Edusemi-Plus |
Applied learning materials analyzing geopolitics, product strategy, AI, quantum technologies, and investment. | - In-depth analysis of Apple Silicon, the CHIPS Act, and Cryo-CMOS - Explores technology within its societal, policy, and industrial context |
| 🎛️ EduController |
Comprehensive coverage from control theory (PID, state-space) to AI control (NN, RL, LLM). | - Linked with PoC design and OpenLane-based control implementation - Design exercises in Python, RTL verification, and FSM generation support |
👤 Author
Author with professional background in semiconductors and inkjet actuators, creating materials that integrate theory and practice.
| 📌 Item | Details |
|---|---|
| Name | Shinichi Samizo |
| Expertise | Semiconductor devices (logic, memory, high-voltage mixed integration) Thin-film piezoelectric actuators for inkjet applications printhead productization, BOM management, and ISO training |
| 💻 GitHub | Samizo-AITL |
📄 License
Adopts a hybrid licensing model according to the nature of the materials, code, and diagrams.
Hybrid licensing based on the nature of the materials, code, and diagrams.
| 📌 Item | License | Description |
|---|---|---|
| Code | MIT License | Free to use, modify, and redistribute |
| Text materials | CC BY 4.0 or CC BY-SA 4.0 | Attribution required, share-alike for BY-SA |
| Figures & diagrams | CC BY-NC 4.0 | Non-commercial use only |
| External references | Follow the original license | Cite the original source |
💬 Feedback
Propose improvements or start discussions via GitHub Discussions.
