🎓 Edusemi-v4x | Foundational Educational Materials for Semiconductor Product Development
🇯🇵 半導体プロダクト開発のための基礎教育教材
🔗 Official Links
| Language | GitHub Pages 🌐 | GitHub 💻 |
|---|---|---|
| 🇺🇸 English |  |
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| 🇯🇵 Japanese |  |
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✍️ Introduction
Semiconductor technology began with the invention of the transistor and rapidly evolved with the advent of the MOS structure.
Miniaturization and integration have progressed in line with Moore’s Law, and LSIs have penetrated all fields.
However, fundamental areas such as physics, circuits, processes, and testing are often fragmented in educational contexts.
In practice, these are closely connected—circuits depend on device physics, and design is supported by process technology and reliability.
Edusemi focuses on the structural connections between fundamental technologies, fostering structural understanding with an eye toward applications.
💡 Design follows physics, and productization follows verification.
Visualizing the connection from physics → circuits → implementation → verification.
📘 Project Overview
Edusemi-v4x is an open educational resource covering the full range from design to manufacturing, testing, and quality assurance.
- 🎯 Target Audience: Engineering students, junior engineers, educators
- ⭐ Features: Emphasis on fundamental interconnections, coverage from design to mass production testing
- 🧪 Practice: sky130, OpenLane, Python, GitHub, ChatGPT integration
🧭 Fundamentals
Systematically covers semiconductor physics, logic design, and process technology—the foundation of all applications.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🧭 1 | Semiconductor Physics & Materials | Band structure, PN junction, MOS field effect |
| 🧭 2 | Digital Logic & Circuit Design | Combinational/sequential circuits, FSM, HDL |
| 🧭 3 | Process Technology & Scaling | Node evolution, interconnect, lithography, reliability |
| 🧭 4 | MOS Characteristics | Dimensions, characteristics, PDK, design rules |
| 🧭 5a | Spec Definition & Interface Design | Upstream process, module selection, PoC connectivity |
| 🧭 5 | SoC Design Flow | RTL, P&R, DRC/LVS, timing |
| 🧭 6 | Test & Packaging | ETEST, failure analysis, reliability testing, shipment |
| 🧭 7 | Design Review & Collaboration | SRAM failure cases, DR structure, consensus building |
🧩 Applications
Builds on fundamentals to cover memory, high-voltage, ESD, and analog/mixed-signal design.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🧩 1 | Memory Technologies | SRAM, DRAM, FeRAM, MRAM |
| 🧩 2 | High-Voltage Devices | LDMOS, field control, high-voltage design |
| 🧩 3 | ESD Protection Design | Protection devices, failure cases, test standards |
| 🧩 4 | Layout Optimization | CMP dummy, IR drop, latch-up |
| 🧩 5 | Analog / Mixed-Signal | Analog design, noise, mixed integration |
| 🧩 5a | 0.18μm AMS Design | Variability, matching, 1/f noise |
| 🧩 5b | AMS Differentiation from Manufacturing | 1/f noise reduction, leveraging manufacturing |
| 🧩 6 | PDK & EDA Environment | DRC/LVS/ERC, PDK structure |
| 🧩 7 | Automation & Verification | OpenLane, CI/CD, lint |
| 🧩 8 | FSM Design | Moore/Mealy, state diagrams, Verilog |
| 🧩 9 | PLL & Clock Design | PLL structure, jitter, STA considerations |
🛠 Practice
Hands-on training through Python automation, Sky130 experiments, and OpenLane implementation.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 🛠 1 | Python Automation Tools | SPICE analysis, OpenLane log processing |
| 🛠 2 | Sky130 Experiments | Vg–Id, Vth estimation, BTI/TDDB evaluation |
| 🛠 3 | OpenLane Practice | Synthesis → P&R → GDS output |
| 🛠 4 | PoC Design Development | FSM, MUX, adder, testing |
| 🛠 5 | Evaluation & Reporting | Area, waveform, timing, DRC/LVS |
📦 Special Topics
Focuses on advanced nodes, chiplets, integrated control SoCs, and other frontier topics.
| 📖 Chapter | 📚 Title | 📝 Summary |
|---|---|---|
| 📦 1 | Advanced Nodes | FinFET, GAA, CFET and their design impacts |
| 📦 2 | Chiplets & Advanced Packaging | 2.5D/3D, TSV, heterogeneous integration |
| 📦 2a | SystemDK Design Constraints | SI/PI, thermal, stress, EMI/EMC |
| 📦 3 | Integrated Control SoC | FSM × PID × LLM (AITL) |
| 📦 4 | OpenLane Implementation | P&R of integrated control RTL |
| 📦 5 | Design for Manufacturability | DRC, LVS, DFM guidelines, Sky130 |
🔗 Related Projects
Sister projects linked with Edusemi, covering control theory, socio-industrial structures, and advanced technologies.
| 🌐 Project | Overview | Key Features |
|---|---|---|
➕ Edusemi-Plus  |
Applied learning materials analyzing geopolitics, product strategy, AI, quantum, and investment. | - In-depth analysis of Apple Silicon, CHIPS Act, and Cryo-CMOS - Explores not only technology but also its societal context and background |
| 🎛️ EduController |
Covers control theory (PID, state-space) to AI control (NN, RL, LLM). | - Linked with PoC design and OpenLane control implementation - Design exercises in Python, RTL verification, FSM generation support |
| 🤖 AITL-H |
Three-layer control architecture: FSM (instinct) + PID (reason) + LLM (intelligence). | - PoC implementation for humanoid robot integrated control - Structurally linked with Edusemi Special Edition Chapters 3 & 4 |
👤 Author
Author with professional background in semiconductors and inkjet actuators, creating materials integrating theory and practice.
| 📌 Item | Details |
|---|---|
| Name | Shinichi Samizo |
| Education | M.Eng., Electrical and Electronic Engineering, Shinshu University |
| Career | Former engineer at Seiko Epson Corporation (1997–) |
| Expertise | Semiconductor devices (logic, memory, high-voltage mixed) Thin-film piezoelectric actuators for inkjet PrecisionCore printhead productization, BOM management, ISO training |
| Contact | ✉️ shin3t72@gmail.com 🐦 https://x.com/shin3t72 💻 https://samizo-aitl.github.io/ |
📄 License
Open license allowing free use for education, research, and corporate training.
| 📌 Item | Details |
|---|---|
| Type | MIT License |
| Usage | Free to use, modify, and redistribute |
| Recommended Uses | Education, research, corporate training |
💬 Feedback & ChangeLog
Propose improvements via GitHub Discussions, and track updates in the ChangeLog.
