✍️ Introduction
The evolution of semiconductor technology began with the invention of the transistor and rapidly accelerated with the advent of the MOS structure.
Driven by Moore’s Law, miniaturization and integration have enabled the proliferation of LSI across all industries.
However, in the real world of engineering, disciplines such as materials science, circuit design, process technology, and testing are often taught in isolation.
In practice, these fields are closely interconnected—circuit behavior relies on device physics, and design feasibility depends on process capabilities and reliability.
Edusemi addresses this gap by focusing on the structural interconnections between foundational technologies.
While maintaining awareness of advanced applications, the emphasis remains on cultivating a deep, structural understanding of core semiconductor technologies—making the knowledge immediately useful in real-world development.
Edusemi-v4x is an open-source educational project designed to teach the fundamentals of semiconductor design, fabrication, testing, and quality assurance in an integrated and practical manner.
| Chapter | Title | Description |
|---|---|---|
| 1 | Fundamentals of Semiconductor Materials | Band structure, PN junctions, MOS field-effect principles |
| 2 | Digital Logic and Circuit Design | Combinational and sequential logic, FSMs, HDL basics |
| 3 | Process Technology and Scaling Limitations | Node evolution, interconnects, lithography, reliability |
| 4 | MOS Transistor Characteristics and Design Foundations | Device dimensions, PDKs, design rules, performance metrics |
| 5 | SoC Design Flow and EDA Tools | RTL design, synthesis, place & route, DRC/LVS, timing analysis |
| 6 | Testing, Packaging, and Productization | ETEST, wafer probing, failure analysis, reliability testing |
| 7 | Design Reviews and Organizational Collaboration | DR structure, case studies, defect examples, consensus building |
| Chapter | Title | Description |
|---|---|---|
| 1 | Memory Technologies | SRAM, DRAM, FeRAM, MRAM—structures, features, and SoC relevance |
| 2 | High-Voltage Devices | LDMOS and field control structures for high-voltage operation |
| 3 | ESD Protection Design | Basics of ESD, protection devices, layout considerations |
| 4 | Layout Design and Optimization | CMP dummy fill, IR drop, latch-up prevention, physical strategies |
| 5 | Analog / Mixed-Signal Design | Analog block design, noise, layout challenges in mixed-signal systems |
| 6 | PDK and EDA Environments | Structure of PDKs, EDA integration, DRC/LVS/ERC workflows |
| 7 | Automation and Verification Techniques | Linting, OpenLane verification, log analysis, CI/CD practices |
| 8 | FSM Design (Finite State Machines) | Moore/Mealy models, state diagrams, Verilog implementation |
| 9 | PLL and Clock Design | PLL architecture, frequency synthesis, jitter/skew, STA considerations |
| Chapter | Title | Description |
|---|---|---|
| 1 | Python Tools for Automation | SPICE simulation, characteristic plotting, OpenLane log analysis |
| 2 | Sky130 Experiments and SPICE Evaluation | Vg–Id curves, threshold voltage (Vth) estimation, BTI/TDDB analysis |
| 3 | Digital Design Practice with OpenLane | RTL-to-GDS flow with synthesis, place & route, and report analysis |
| 4 | PoC Specifications and Design Expansion | FSM, MUX, Adder—PoC specs and Verilog implementation with testbenches |
| 5 | Evaluation and Reporting of Design Results | Waveform, area/timing/DRC evaluation and improvement proposals |
| Chapter | Title | Description |
|---|---|---|
| 1 | Advanced Nodes (FinFET, GAA, etc.) | Physics and design impacts of next-gen transistors |
| 2 | Chiplet and Advanced Packaging Technologies | 2.5D/3D integration, TSVs, interposers in heterogeneous systems |
| 3 | SoC Implementation of FSM × PID × LLM Control System | Application of AITL architecture in integrated control SoCs |
| 4 | OpenLane-Based RTL-to-GDSII Implementation of Control Systems | Layout and DRC of integrated control logic |
| 5 | Physical Verification and DFM Strategies | DRC/LVS/DFM techniques using Sky130 PDK |
| 6 | Piezo Actuator Control System Design | Polarization, hysteresis compensation, FSM control, COF implementation |
| 7 | Product Documentation and Workflow in Final Products | BOM management, prototyping, evaluation, DR & mass production gates |
Edusemi is designed with ChatGPT integration as a learning partner.
Learners can get support in code reviews, error diagnostics, tool usage, conceptual explanations, experiment reporting, and more.
This interactive and industry-aligned approach bridges theory and practice—preparing learners for modern semiconductor development.
A comprehensive control education platform covering classic PID, modern state-space, H∞, and AI control (NN, RL, LLM integration).
A hybrid intelligent control framework combining FSM (instinct), PID (reason), and LLM (intelligence).
An applied extension of Edusemi focused on geopolitics, market trends, corporate strategies, and emerging technologies.
This project is released under the MIT License.
Free to use, modify, and redistribute. Educational and corporate training use is welcome.