🧭 Legacy Technology

Legacy Technology is not a collection of obsolete processes.

This archive documents canonical failure-and-recovery cases in which physical mechanisms directly constrained yield, reliability, and ultimately business decisions.

These cases are preserved not as nostalgia, but as reference structures—patterns of causality that continue to reappear in modern semiconductor systems, SoCs, and AI-integrated architectures.

🔗 Links

Language	GitHub Pages 🌐	GitHub 💻
🇺🇸 English

🔐 Note on Confidentiality

All materials in this archive are based on semiconductor technologies
developed more than 20 years ago (late 1990s–early 2000s).

This archive does not contain:

• Proprietary process recipes
• Confidential design rules
• Equipment tuning parameters
• Operational know-how applicable to current manufacturing

The purpose is to preserve
structural patterns of failure, recovery, and decision-making,
not implementation-level secrets.

This archive is intended for education, analysis, and architectural reference.

📘 Introduction

The philosophy and positioning of Legacy Technology are explained in detail here:

→ Introduction — Legacy Technology

🎯 Scope of This Archive

This archive focuses on the intersection of process physics, manufacturability, and strategic decision-making.

• 🏗 Semiconductor process integration (1990s–2000s)
• 💾 Memory technologies (DRAM, PSRAM, eDRAM)
• ⚛️ Failure physics (leakage, disturb, retention)
• 📈 Yield recovery under constraints
• 🧠 Engineering decisions under business pressure

The emphasis is on causal structure, not historical completeness.

🧭 How to Read This Archive

Each case is organized as a causal chain:

1. Process / Structure
2. Observed Failure Mode
3. Physical Root Cause
4. Test / Bin Manifestation
5. Yield Recovery or Strategic Decision

This order mirrors actual manufacturing problem-solving, not post-hoc academic explanation.

📌 Readers are encouraged to follow the chain, not jump directly to conclusions.

📂 Case Index

💾 DRAM (0.25µm, 64M) — 3rd Generation

A canonical baseline case exposing retention, leakage, and test–yield coupling before deep-submicron scaling.

• Case overview
  → dram_025um/
• Process integration
  → dram_025um/process_flow.md
• Wafer test & bin classification
  → dram_025um/wafer_test_bin.md
• Failure physics (Pause / Disturb)
  → dram_025um/pause.md

📱 PSRAM (Pseudo-SRAM, 2001) — Mobile Memory

A boundary case where DRAM technology was pushed beyond its original operating envelope to meet mobile requirements.

• Case overview
  → psram_2001/
• Architecture & concept
  → psram_2001/psram_architecture.md
• Pause / Disturb under mobile usage
  → psram_2001/pause_disturb_psram.md
• Yield recovery & countermeasures
  → psram_2001/yield_recovery.md

🧱 Positioning

Legacy Technology cases are archived here because they expose structural limits—not because they are old.

Modern systems often fail for the same reasons: only the scale, terminology, and integration context change.

📌 Understanding these patterns is essential for designing robust modern systems.

Author

📌 Item	Details
Name	Shinichi Samizo
Expertise	Semiconductor devices (logic, memory, high-voltage mixed-signal) Thin-film piezo actuators for inkjet systems PrecisionCore printhead productization, BOM management, ISO training
GitHub

License