【Semiconductor】17. The Physical Origin of Pause Refresh Anomalies in 0.25 µm DRAM

topics: [“Semiconductor”, “DRAM”, “Failure Analysis”, “Device Physics”, “Process”]

🧭 Introduction

In the previous article,
we recorded only the phenomenology of the anomalies observed under Pause Refresh conditions
in 0.25 µm generation DRAM.

In this article, we organize
which physical behaviors those phenomena corresponded to.

To state the conclusion upfront,
this was not a phenomenon that could be summarized simply as “poor retention.”

The dominant factor was neither cell capacitance nor circuitry,
but process-induced leakage physics.

🔍 Physical Clues Indicated by the Observations

The observed facts listed in the previous part
all pointed in the same direction.

The physical conditions that satisfy all of these simultaneously are limited.

  1. Occurring locally
  2. Thermally activated
  3. Not permanent destruction

At this point,
the dominant factor had been narrowed down to almost a single candidate.

🎯 Dominant Factor: Junction Leakage

The true nature of the Pause Refresh anomaly was
junction leakage current in the cell MOS transistors.

In particular, the dominant contribution came from
defect-assisted leakage levels located near:

🧬 Cross-Sectional Structure Where Leakage Occurs (Reference)

Here, a cross-sectional diagram serving as the physical premise
for understanding the Pause Refresh anomaly is shown.

Figure 1: Junction-edge leakage paths in a 0.25 µm DRAM cell (conceptual cross-section)

What this diagram illustrates is that
leakage is concentrated not across the entire cell,
but at very localized structural edges.

All of these are locations where
process-induced damage tends to accumulate.

🔁 Behavior Governed by SRH Recombination

This leakage was governed by
Shockley–Read–Hall (SRH) recombination.

The characteristics of SRH leakage are well defined:

These characteristics naturally explain the reversible behavior whereby:

🎲 Why Do Failures Appear as “Random Single Bits”?

SRH leakage is not:

Defects are:

As a result:

They are therefore observed as
random single-bit failures.

🚫 Cell Capacitance Was Not the Cause

This was a critical turning point.

The Pause Refresh anomaly could not be explained by:

Even when capacitance was increased:

Retention time was determined by leakage,
not by capacitance.

🧪 Strong Correlation with Process History

The failure rate showed
strong correlation with specific process conditions.

Representative examples include:

All of these act in the direction of:

Increasing interface defect density

When process conditions were modified, failures decreased;
when reverted, failures reappeared.

This reproducibility was
decisive evidence of a physics-driven origin.

⏸ Why Did It Manifest Only Under Pause Conditions?

During normal operation or regular refresh:

make leakage difficult to observe.

Under Pause Refresh conditions:

As a result:

Leakage current × no-replenishment time

directly manifests as data loss.

Pause Refresh was therefore
a condition that exposed leakage physics directly.

🧾 Summary (Physics)

The Pause Refresh anomaly in 0.25 µm DRAM was:

It was leakage physics created by process-induced defects.

From the outset,
this phenomenon was never something to be debated at the design level.

🔗 Primary Sources (References)

⏭ Next

From the next article onward,
we will move on to the PSRAM (2001) case.

First, we will address only
what PSRAM was intended to achieve
—its structure and assumptions.