🔢 Fixed-Point Design for V–I Control

This chapter explains how continuous-valued control equations are mapped into fixed-point arithmetic suitable for a deterministic digital ASIC implementation.

All voltage V and current I signals are treated explicitly as fixed-point numbers, with bounded range and known precision.

🎯 Why Fixed-Point?

Floating-point arithmetic is avoided in this design because:

• Hardware cost is high
• Latency is variable
• Verification becomes complex

Fixed-point arithmetic provides:

• Deterministic execution time
• Predictable overflow behavior
• Efficient hardware implementation

These properties are essential for control and safety-critical systems, where timing and numerical behavior must be provable.

📐 Signal Normalization (V–I)

Before entering the control core, all physical signals are normalized.

Voltage

Let the physical voltage range be:

The normalized digital voltage is defined as:

Current

Similarly, for current:

After normalization:

• $V[n] \in [0, 1]$
• $I[n] \in [0, 1]$

This ensures that all subsequent fixed-point computations operate on bounded, dimensionless quantities.

🧩 Fixed-Point Data Path (Conceptual)

The fixed-point data path is defined before RTL coding to make numerical behavior explicit and analyzable.

V[n], I[n]  (Q1.15)
   │
   ▼
Error computation
e[n] = V_ref[n] − V[n]      (Q2.15)
   │
   ▼
+----------------------+
| PID Computation      |
|  - P term            |
|  - I accumulator     |
|  - D term (optional) |
+----------------------+
   │   (bit growth)
   ▼
Saturation & truncation
   │
   ▼
u[n]  (Q2.15)
   │
   ▼
PWM mapping

This conceptual data path explicitly defines:

• where bit growth occurs
• where saturation is applied
• which signals are stored as state

RTL waveforms confirming this behavior are provided in
Appendix A: Figure List.

🧮 Q-Format Representation

A fixed-point number is represented as:

where:

• $f$ : number of fractional bits

Example: Q1.15 Format

• Total bits: 16
• Integer bits: 1
• Fractional bits: 15

Range:

Resolution:

This format is well suited for normalized V and I signals.

⚙️ Fixed-Point PID Computation

The discrete-time PID equation:

is implemented using fixed-point multipliers and adders.

Gain Representation

• $K_p$, $K_i$, $K_d$ are stored as fixed-point values
• Gains are programmable via registers (SPI)
• Gain changes do not affect control timing

Care must be taken to allocate sufficient bit width for intermediate multiplication results.

🚨 Saturation and Overflow Handling

Unlike software, hardware must explicitly define behavior when numerical limits are exceeded.

Saturation Policy

If a computed value exceeds the allowed range:

• Positive overflow → clamp to maximum
• Negative overflow → clamp to minimum

This avoids wrap-around behavior, which can cause catastrophic instability in control systems.

All saturation points are explicitly coded in RTL.

📊 Bit-Width Planning (Example)

These values are design examples, chosen to illustrate:

• headroom for accumulation
• bounded control output
• safe saturation margins

Actual formats may be adjusted based on system requirements.

⏱ Deterministic Latency

Each fixed-point operation:

• Uses a known number of clock cycles
• Has no data-dependent timing

Therefore, the total control latency is:

This makes worst-case timing trivial to compute and verify.

🧪 Verification Strategy

Fixed-point behavior is verified by:

• Comparing against floating-point reference models
• Explicitly testing saturation and overflow cases
• Inspecting waveforms for bit growth and truncation

This ensures numerical correctness before synthesis.

➡️ Next

Proceed to RTL implementation:

➡️ RTL: PID Core

The next chapter maps the control equations directly into synthesizable Verilog RTL.

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