18_STA_Reality_and_Timing_Closure.md

When Slack Becomes Law

Purpose of This Chapter

This chapter explains what Static Timing Analysis (STA) really is
and why, in ASIC design, timing results override intuition, simulation, and hope.

If STA says “fail”, the chip fails.

There are no exceptions.

Why STA Is the Final Judge

RTL simulation answers:

“Does this logic behave functionally?”

STA answers:

“Will this logic meet timing in silicon under physics?”

Only one of these decides whether a chip works after fabrication.

That one is STA.

What STA Actually Analyzes

STA evaluates all possible timing paths without simulation vectors.

It considers:

• Cell delays (from .lib)
• Wire delays (from SPEF)
• Clock tree structure
• Setup and hold constraints
• Process / voltage / temperature corners

STA does not care about your intent.
It only cares about numbers.

The Meaning of Slack

Slack is defined as:

slack = required_time − arrival_time

Interpretation:

• Positive slack → timing satisfied
• Zero slack → razor edge
• Negative slack → guaranteed failure

There is no “almost okay”.

Setup vs Hold (Reality Version)

Setup Violation

• Data arrives too late
• Clock period is too short
• Typically fixed by:
  • Pipelining
  • Faster cells
  • Shorter routes

Hold Violation

• Data arrives too early
• Often caused by:
  • Clock skew
  • Over-optimization
• Fixed by:
  • Delay insertion
  • Buffer balancing

Hold violations are more dangerous: they can break even at low frequencies.

Why Simulation Cannot Replace STA

Simulation:

• Uses specific vectors
• Misses rare paths
• Ignores worst-case alignment

STA:

• Explores all paths
• Assumes worst-case alignment
• Is intentionally pessimistic

Pessimism is not a bug. It is safety margin.

Clock Tree Reality

The clock is not ideal.

In real silicon:

• Clock arrival differs per register
• Buffers add delay and skew
• Routing geometry matters

CTS exists to manage this chaos.

STA evaluates the actual clock tree, not the imagined one.

Understanding Reports (What Actually Matters)

Key reports to read:

• Worst Negative Slack (WNS)
• Total Negative Slack (TNS)
• Critical path breakdown
• Launch / capture clocks
• Cell and wire contribution

Ignore summary numbers until you understand the path.

The Critical Path Fallacy

The “critical path” is not:

• The longest RTL path
• The most complex logic
• The path you expect

It is the path STA finds.

Always trust the report, not your intuition.

Why Timing Closure Is Hard

Timing closure is hard because:

• Physical placement affects delay
• Routing congestion affects delay
• Clock tree affects everything
• Fixing one path breaks another

This is normal.

Acceptable Timing Philosophy

Production-quality rules:

• WNS ≥ 0 at all corners
• Hold clean at all corners
• No waived violations
• No “it probably works”

If timing is not closed:

The chip is unfinished.

Common Timing Myths

Myth 1: “It works at lower frequency”

False. Hold violations ignore frequency.

Myth 2: “We’ll fix it in ECO”

False. ECOs still obey physics.

Myth 3: “Simulation passed”

Irrelevant.

Practical STA Workflow

1. Trust STA first
2. Read path details
3. Identify dominant contributors
4. Fix structurally, not cosmetically
5. Re-run STA
6. Repeat until clean

There is no shortcut.

Chapter Conclusion

• STA is law, not advice
• Slack is binary: pass or fail
• Simulation cannot override physics
• Timing closure defines “done”

Next Chapter

Now that timing reality is understood, we connect it back to simulation.

👉 19_GLS_with_SDF_When_Waveforms_Tell_the_Truth.md — Timing in Motion