11_STA.md

Static Timing Analysis — Timing Is a Contract


Purpose of This Chapter

Static Timing Analysis (STA) is not a suggestion system.

It is a contract.

If STA says the design does not meet timing, the design is invalid, regardless of simulations or intentions.


What STA Actually Answers

STA answers one question only:

Will every signal arrive before it is required, under worst-case assumptions?

It does not simulate behavior. It does not care about functional correctness.

It only cares about time.


The Timing Contract

Every timing path is defined by:

If:

arrival_time ≤ required_time

The path passes.

If not, the chip fails.


Key STA Terms (No Hand-Waving)

Setup Slack

Hold Slack

Both matter. Passing setup but failing hold is still failure.


Why Simulation Cannot Replace STA

Simulation:

STA:

Real silicon obeys STA, not simulation optimism.


Reading STA Reports Correctly

Never start with averages.

Always start with:

If WNS < 0: stop.


The Most Common STA Mistake

“It only fails by a little.”

There is no “a little” in silicon.

A −10 ps violation is as real as −1 ns.


Clock problems dominate STA failures:

Fix clocks first. Always.


Data Path Failures

Common causes:

These are architectural problems, not tool problems.


Hold Violations Are Not Optional

Hold violations:

Ignoring hold violations guarantees silicon failure.


STA Before and After Routing

Pre-route STA:

Post-route STA:

Only post-route STA matters.


What STA Is Not

STA is the law.


When to Roll Back

Immediately roll back if:

Fix the cause, not the report.


Healthy STA Indicators

A healthy design shows:

Anything else is a warning.


Why This Chapter Exists

Many designs “work” in simulation.

They still fail in silicon.

STA is how silicon speaks back.


Next Chapter

After timing is clean: