๐ผ GDS Screenshot Index
This page lists all screenshot PNGs generated during the
GF180 HV layout and GDS-oriented exploration.
Each image corresponds to a concrete GDS artifact and a
documented Run or structural milestone.
This index exists purely to make visual inspection fast and unambiguous.
๐งฐ Environment

- ๐ฅ KLayout environment used for all manual and macro-based layout work
๐งฑ HV_SW_UNIT โ Single / Array (Baseline)

- โก Single HV_SW_UNIT with DNWELL and guard ring

- ๐งฉ Naive array with per-unit DNWELL and guard ring
- โ Pitch dominated by guard ring enclosure
๐ Guard Ring Sharing Study

- ๐งช Column-wise guard ring sharing (intermediate state)

- ๐งน Guard-ring-clean shared configuration
- ๐ Guard ring no longer dominant pitch limiter
๐ก 300 dpi Array (Golden Baseline)

- ๐ 300 dpi (~85 ยตm pitch) array
- โ
Structurally feasible under GF180 DNWELL constraints
- โญ Treated as golden baseline
๐งช Run 001 โ Probe Layout

- ๐ Aggressive probe layout to expose dominant HV constraints
๐งช Run 002 โ Guard Strategy Change

- ๐ Per-cell guard ring โ shared outer guard ring
๐งช Run 003 โ Poly Gate Trim

- โ Poly gate end isolation study
- ๐ Guard ring no longer pitch-dominant
๐งช Run 004 โ X-Direction Tiling Evaluation

- ๐งญ X-tiling evaluation based on Run 003

- ๐ 16 ยตm pitch confirmed geometrically feasible (marginal)

- ๐งฒ Metal1 stub trim, 16 ยตm pitch

- โ Metal1 stub trim, 12 ยตm pitch

- โ Metal1 stub trim, 14 ยตm pitch
HV Inverter 1ch Unit (300dpi)

๐ Notes
- ๐ผ All images are direct screenshots from KLayout
- ๐ซ No DRC / LVS deck was applied (layout-first exploration)
- ๐ Image order matches RUNNING_LOG progression
- ๐ This index is purely visual and contains no design intent beyond what is logged
End of document.