πŸ“˜ BSIM4_ANALYZER_DC


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Automated DC Analysis Tool for BSIM4 MOSFET Models (Vg–Id / Vd–Id)

This tool was originally developed for semiconductor device engineering education,
but is also designed with future commercial MOSFET parameter analysis applications in mind.

The system currently supports 130nm CMOS (NMOS/PMOS).
The folder results/90nm/ is intentionally empty and reserved for future feature expansion.
Extending the current 130nm analysis flow to 90nm is straightforward.


πŸ“š Features


πŸ“ Directory Structure

BSIM4_ANALYZER_DC/
β”œβ”€β”€ models/
β”‚   β”œβ”€β”€ nmos130.sp
β”‚   └── pmos130.sp
β”‚
β”œβ”€β”€ templates/
β”‚   β”œβ”€β”€ template_vgid.cir
β”‚   └── template_vdid.cir
β”‚
β”œβ”€β”€ run/
β”‚   β”œβ”€β”€ run_vgid.py
β”‚   └── run_vdid.py
β”‚
β”œβ”€β”€ plot/
β”‚   β”œβ”€β”€ plot_vgid.py
β”‚   └── plot_vdid.py
β”‚
β”œβ”€β”€ results/
β”‚   β”œβ”€β”€ 130nm/
β”‚   β”‚   β”œβ”€β”€ vgid/
β”‚   β”‚   └── vdid/
β”‚   └── 90nm/           # ← Reserved for future expansion
β”‚
β”œβ”€β”€ bsim4.out
└── README.md

πŸš€ Usage

β–  Requirements


β–  Running Simulations

● Vg–Id (VGID)

python run/run_vgid.py

● Vd–Id (VDID)

python run/run_vdid.py

β–  Generating Plots

● Vg–Id

python plot/plot_vgid.py

● Vd–Id

python plot/plot_vdid.py

πŸ“Š Output Files (with extracted parameters)

The tool processes raw ngspice .dat files and automatically extracts
important DC parameters, saving them as CSV files.


β–  VGID Parameter Extraction (Vg–Id)

Parameter Description Method
Vth (gmmax method) Threshold voltage Vg at gm maximum
gmmax Maximum transconductance max(dId/dVg)

CSV example:

device,corner,Vth_gmmax,gmmax
nmos,HT,0.478,0.00123
pmos,RT,-0.512,0.00101

β–  VDID Parameter Extraction (Vd–Id)

Parameter Description Method
Idlin Linear-region Id Low-Vd current (e.g., 50 mV)
Idsat Saturation-region Id High-Vd current (β‰ˆ Vdd)

CSV example:

device,corner,Idlin,Idsat
nmos,LT,1.23e-5,2.88e-4
pmos,RT,-9.88e-6,-2.42e-4

πŸ“¦ Output File Types

Example:

130nm_nmos_vgid_HT.csv
130nm_nmos_vgid_log.png
130nm_pmos_vdid_LT.csv
130nm_pmos_vgid_lin.png

🧩 Parameter Extraction Algorithms

● Vth (gmmax method)

  1. Load Id–Vg curve
  2. Compute gm = dId/dVg
  3. Identify Vg where gm is maximum β†’ Vth
  4. Record gmmax

● Idlin / Idsat


πŸ”§ 90nm Node (Future Extension)

results/90nm/ is reserved for expansion.
To add 90nm support, simply:

The structure is intentionally built for future commercial scalability.


πŸ“ˆ Example Plots Generated by BSIM4_ANALYZER_DC

The following figures are automatically produced by the
BSIM4 DC Analyzer (Vg–Id / Vd–Id) for 130nm NMOS/PMOS devices.
They demonstrate the tool’s ability to generate device characteristics
across temperature corners (LT / RT / HT).


β–Ά NMOS β€” Vg–Id (VGID, Linear Region)

Shows the gate-voltage sweep (Id–Vg) under linear Vd bias for NMOS,
revealing threshold voltage and mobility temperature dependence.


β–Ά NMOS β€” Vd–Id (VDID)

Illustrates output characteristics (Id–Vd) at fixed Vgs,
showing linear-to-saturation transition.


β–Ά PMOS β€” Vg–Id (VGID, Linear Region)

The PMOS transfer curve, plotted with SPICE polarity,
showing temperature effects on |Vth| and hole mobility.


β–Ά PMOS β€” Vd–Id (VDID)

PMOS output characteristics (Id–Vd), SPICE-polarity plotted.
Useful for extracting Idlin/Idsat and channel-length modulation trends.


These plots serve as reference examples for BSIM4 parameter exploration,
educational MOSFET modeling exercises, and future integration into
commercial MOSFET analysis tools.


πŸ“„ Hybrid License

This repository adopts a Hybrid License model:

Item License Description
Source Code MIT License Free to use, modify, and redistribute
Documentation / Text Materials CC BY 4.0 Attribution required
Figures / Plots / Generated Images CC BY-NC 4.0 Non-commercial use only
External References Original license applies Cite properly

πŸ“Œ To-Do / Future Development


πŸ‘€ Author

πŸ“Œ Item Details
Name Shinichi Samizo
GitHub GitHub