MOSFET C–V Extraction Tool (BSIM4, ngspice)


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This tool automatically extracts gate capacitance (Cgg–Vg) characteristics
from BSIM4 NMOS/PMOS models using ngspice DC analysis.

Key features:


πŸ“ Directory Structure

BSIM4_ANALYZER_CV/
β”‚
β”œβ”€β”€ models/
β”‚   β”œβ”€β”€ nmos130.sp
β”‚   └── pmos130.sp
β”‚
β”œβ”€β”€ template_cv.cir
β”œβ”€β”€ run_cv.py
β”œβ”€β”€ plot_cv.py
β”œβ”€β”€ README.md
β”‚
└── results/
    └── 130nm/
        β”œβ”€β”€ nmos_130nm_RT.cir
        β”œβ”€β”€ nmos_130nm_RT.log
        β”œβ”€β”€ nmos_130nm_RT.png
        β”œβ”€β”€ pmos_130nm_RT.cir
        β”œβ”€β”€ pmos_130nm_RT.log
        β”œβ”€β”€ pmos_130nm_RT.png
        └── … (LT / HT also produced)

🧩 1. template_cv.cir (Analysis Template)

A voltage sweep template used by Python .format() to embed settings.

NMOS (standard)

PMOS (real device behavior)

Output: Cgg only

.print dc V(g) @m1[cgg]

❗ Why Only Cgg Is Extracted (Important)

BSIM4 internal capacitances behave as:

Problems with partitioned capacitances:

β†’ Therefore, this tool extracts Cgg only, ensuring physical interpretability.


πŸš€ 2. Netlist Auto-Generation & Batch Execution (run_cv.py)

Run:

python run_cv.py

This performs:

Update ngspice path if needed:

NGSPICE_CMD = r"C:\Program Files\Spice64\bin\ngspice.exe"

πŸ“Š 3. Plotting Cgg–Vg (plot_cv.py)

Run:

python plot_cv.py

Processing steps:

  1. Read V(g) and Cgg from .print dc
  2. Remove index=0 (DC initial non-physical point)
  3. Remove Cgg ≀ 0 (solver startup noise)
  4. Save PNG to:
results/<node>/<basename>.png

πŸ§ͺ Example Output Behavior


πŸ“¦ Model Files (models/*.sp)

BSIM4 educational models:

(Not matched to any foundry process; intended for learning & analysis.)


πŸ”§ Adding a New Process Node

Add a node definition inside run_cv.py:

"90nm": {
    "vdd": 1.0,
    "nmos_model_file": "nmos90.sp",
    "pmos_model_file": "pmos90.sp",
    "nmos_model_name": "nmos90",
    "pmos_model_name": "pmos90",
    "lch": "0.09u",
    "wch": "1u",
    "toxe": "1.8e-9",
},

βœ” Environment


πŸ“˜ Summary

This tool provides:

  1. Correct terminal conditions for NMOS/PMOS and physically accurate sweep directions
  2. Physically meaningful extraction of Cgg only
  3. Fully automated batch processing for 6 conditions (NMOS/PMOS Γ— 3 temperatures)
  4. Clean separation of models / template / results for easy scaling
  5. Complete automation from ngspice β†’ log β†’ PNG

Ideal for device physics education, compact modeling, and process comparison studies.

Possible extensions:


β–  NMOS C–V Characteristics (130nm, RT)


β–  PMOS C–V Characteristics (130nm, RT)


πŸ“„ Hybrid License

This project uses a Hybrid License:

Item License Description
Source Code MIT License Free to use, modify, redistribute
Documentation / Text Materials CC BY 4.0 Attribution required
Figures / Plots / Generated Images CC BY-NC 4.0 Non-commercial use only
External References Original license applies Cite appropriately

πŸ‘€ Author

πŸ“Œ Item Details
Name Shinichi Samizo
GitHub GitHub