🧾 Unified Transistor and Resistor Summary
Process Node: 0.18μm CMOS / Gate Width $W = 10\mu\mathrm{m}$
This document summarizes:
- Transistor characteristics (NMOS / PMOS) for 1.8V, 3.3V, and 5.0V operation
- Sheet and contact resistances for diffusions, polysilicon, and metals
- $T_{\text{ox}}$ values per voltage domain
📐 Gate Oxide Thickness by Voltage
酸化膜厚と電圧の関係
| Voltage | $T_{\text{ox}}$ (nm) | Notes |
|---|---|---|
| 1.8V | ~3.5 | Core logic transistors |
| 3.3V | ~7.0 | I/O and ESD protection |
| 5.0V | ~15.0 | Analog / high-voltage blocks |
📎 Dielectric: SiO₂ assumed ( $\varepsilon_{\text{ox}} \approx 3.9$ )
🔋 Transistor Characteristics (W = 10μm)
各電圧領域におけるNMOS / PMOS特性
| VDD | $L$ (μm) | Device | $T_{\text{ox}}$ (nm) | $V_{\text{th}}$ (V) | $I_{\text{dlin}}$ (μA/μm) | $I_{\text{dsat}}$ (μA/μm) | $I_{\text{off}}$ (nA/μm) | $I_{\text{cutoff}}$ (pA/μm) | $B_{\text{vds}}$ (V) |
|---|---|---|---|---|---|---|---|---|---|
| 1.8V | 0.16 | NMOS | 3.5 | 0.42 | 300.0 | 500.0 | 100.00 | 1000.0 | 1.60 |
| 1.8V | 0.16 | PMOS | 3.5 | 0.62 | 150.0 | 250.0 | 80.00 | 800.0 | 1.60 |
| 1.8V | 0.18 | NMOS | 3.5 | 0.42 | 298.8 | 498.0 | 92.31 | 941.8 | 1.68 |
| 1.8V | 0.18 | PMOS | 3.5 | 0.62 | 149.4 | 249.0 | 73.85 | 753.4 | 1.68 |
| 3.3V | 0.25 | NMOS | 7.0 | 0.68 | 120.0 | 200.0 | 20.00 | 50.0 | 3.50 |
| 3.3V | 0.25 | PMOS | 7.0 | 0.88 | 60.0 | 100.0 | 16.00 | 40.0 | 3.50 |
| 5.0V | 2.0 | NMOS | 15.0 | 1.00 | 100.0 | 150.0 | 5.00 | 20.0 | 8.00 |
| 5.0V | 2.0 | PMOS | 15.0 | 1.20 | 50.0 | 75.0 | 4.00 | 16.0 | 8.00 |
🧿 Estimated Mobility Table
キャリア移動度（参考）
| Carrier Type | $\mu$ (cm²/V·s) | Notes |
|---|---|---|
| Electron (NMOS) | ~450 | Inversion layer, effective mobility |
| Hole (PMOS) | ~200 | ~0.45× NMOS (typical) |
🧪 Sheet Resistance (Ω/□)
シート抵抗（ポリ・拡散・金属層）
| Structure | $R_{\text{sheet}}$ (Ω/□) | Notes |
|---|---|---|
| N+ Diffusion | ~70 | Shallow implant, moderate Rs |
| P+ Diffusion | ~100 | Higher resistivity |
| N+ Poly | ~60 | Doped polysilicon |
| P+ Poly | ~80 | Higher than N+ poly |
| ALA (Metal-1) | ~0.05–0.08 | Core routing |
| ALB / HLA (Metal-2) | ~0.03–0.06 | Intermediate routing |
| ALC / HLB (Metal-3) | ~0.02–0.05 | Power stripe, major signal distribution |
| ALD / HLC (Metal-4) | ~0.015–0.03 | Pad-level or wide global power bus |
🔧 Contact Resistance
コンタクト抵抗
| Contact Type | $R_{\text{contact}}$ (μΩ·cm²) Kelvin |
$R_{\text{chain}}$ (Ω) 10 elements |
Notes |
|---|---|---|---|
| CNT (N+ Poly) | ~1.2 | ~90 | Gate contact (N+ Poly → W plug) |
| CNT (P+ Poly) | ~1.6 | ~130 | Gate contact (P+ Poly → W plug) |
| CNT (N+ Diff) | ~1.0 | ~80 | Source/Drain contact (N+ Diff → W plug) |
| CNT (P+ Diff) | ~1.4 | ~110 | Source/Drain contact (P+ Diff → W plug) |
| HLA | ~0.8 | ~80 | W plug to Metal-2 (ALA layer) |
| HLB | ~0.7 | ~70 | W plug to Metal-3 (ALB layer) |
| HLC | ~0.6 | ~60 | W plug to Metal-4 (ALC layer, global power bus) |
📎 $R_{\text{contact}}$ is the intrinsic contact resistance per unit area (Kelvin measurement).
$R_{\text{chain}}$ represents total resistance of 10 serial contacts in test structures.
🧮 MOS Capacitor Characteristics (Reference)
酸化膜厚と容量の関係（参考）
| Voltage | $T_{\text{ox}}$ (nm) | $C_{\text{ox}}$ (fF/μm²) | Total Cap (10μm × 10μm) | Notes |
|---|---|---|---|---|
| 1.8V | 3.5 | ~10.0 | ~1000 fF (1.0 pF) | Core device level |
| 3.3V | 7.0 | ~5.0 | ~500 fF | I/O buffer use |
| 5.0V | 15.0 | ~2.3 | ~230 fF | Analog / HV block |
🔍 Calculation Note:
\[C_{\text{ox}} = \frac{\varepsilon_0 \cdot \varepsilon_{\text{ox}}}{T_{\text{ox}}}\]
The gate oxide capacitance per unit area is calculated as:where:
- $\varepsilon_0 = 8.854 \times 10^{-14}~\mathrm{F/cm}$ (vacuum permittivity)
- $\varepsilon_{\text{ox}} \approx 3.9$ for SiO₂
- $T_{\text{ox}}$ is in cm
Thus:
\[C_{\text{ox}} \approx \frac{3.45 \times 10^{-13}}{T_{\text{ox}}~[\mathrm{cm}]}\]For $T_{\text{ox}} = 3.5~\mathrm{nm} = 3.5 \times 10^{-7}~\mathrm{cm}$:
\[C_{\text{ox}} \approx \frac{3.45 \times 10^{-13}}{3.5 \times 10^{-7}} = 9.86 \times 10^{-7}~\mathrm{F/cm^2}\]Convert to fF/μm² (1 F/cm² = 10 fF/μm²):
\[C_{\text{ox}} \approx 9.86~\mathrm{fF}/\mu\mathrm{m}^2\]💡 Result:
When $T_{\text{ox}} = 3.5$ nm, then $C_{\text{ox}} \approx \mathbf{9.86~\mathrm{fF}/\mu\mathrm{m}^2}$.
📏 Units and Symbols
単位と記号の凡例
| Symbol | Unit | Meaning |
|---|---|---|
| $W$ | μm | Gate width |
| $L$ | μm | Gate length |
| $T_{\text{ox}}$ | nm | Gate oxide thickness |
| $I_{\text{dlin}}$ | μA/μm | Linear-region drain current |
| $I_{\text{dsat}}$ | μA/μm | Saturation-region drain current |
| $I_{\text{off}}$ | nA/μm | Off-state leakage current |
| $I_{\text{cutoff}}$ | pA/μm | Subthreshold leakage |
| $B_{\text{vds}}$ | V | Drain-source breakdown voltage |
| $R_{\text{sheet}}$ | Ω/□ | Sheet resistance |
| $R_{\text{contact}}$ | μΩ·cm² | Contact resistance (Kelvin) |
| $R_{\text{chain}}$ | Ω | Contact chain resistance (10×) |
| $C_{\text{ox}}$ | fF/μm² | Gate oxide capacitance density |
📚 Basis of Parameters and Estimation Methods
出力根拠と補足 / Basis of Parameter Derivations
本ドキュメントで示された各種パラメータは、以下の資料、推定手法、ならびに物理モデルに基づいて構成されています：
The parameters presented in this document are derived based on the following data sources, estimation methods, and physical models:
1. 📖 公開プロセス資料・ベンダーデータ
Public Process References and Vendor Data
以下のような代表的なソースから抽出・整理された実データを反映しています：
Representative sources used for extracting and consolidating actual data include:
- TSMC / UMC / TowerJazz / GlobalFoundries 等の 0.18μm PDKやプロセス概要資料
→ 0.18μm PDKs and process documentation from vendors such as TSMC, UMC, TowerJazz, GlobalFoundries - IEDM, VLSI Symposia 等で発表された論文ベースの標準トランジスタ特性
→ Published transistor characteristics in IEDM, VLSI Symposia, and related technical papers - TI / ADI / NXPなどアナログ回路向け0.18μm世代のプロセスデータシート
→ Datasheets from analog IC vendors like TI, ADI, NXP based on 0.18μm CMOS processes
2. 🔬 モデルベースの推定補完（ゲート幅 $W = 10\mu\mathrm{m}$ で正規化）
Model-Based Estimation (Normalized for $W = 10\mu\mathrm{m}$)
一部のパラメータは、以下のようなMOSトランジスタの基本モデルに基づき推定しています：
Some parameters are estimated using fundamental MOS transistor models, normalized to a gate width of $W = 10\,\mu\mathrm{m}$:
🔍 この式は、MOSトランジスタが 飽和領域（ $V_{\text{ds}} > V_{\text{gs}} - V_{\text{th}}$ ） で動作する場合の電流値近似式であり、CMOS設計における基本的な電流モデルです。
🔍 This formula approximates the drain current when the MOS transistor operates in the saturation region ($V_{\text{ds}} > V_{\text{gs}} - V_{\text{th}}$), and serves as a fundamental current model in CMOS design.
- $I_{\text{dlin}}$ は $V_{\text{ds}}$ が小さいときの近似値として評価
→ $I_{\text{dlin}}$ is estimated under small $V_{\text{ds}}$ (linear region) - PMOS 特性は、NMOSの $\sim 0.5 \times$ 程度でスケーリングして推定
→ PMOS values are estimated by scaling NMOS data by approximately $\sim 0.5 \times$ - 閾値電圧（ $V_{\text{th}}$ ）、酸化膜厚（ $T_{\text{ox}}$ ）、リーク電流（ $I_{\text{off}}$ ）などは、物理整合性およびLeakage対策を考慮して設定
→ Threshold voltage ($V_{\text{th}}$), oxide thickness ($T_{\text{ox}}$), and leakage current ($I_{\text{off}}$) are chosen based on physical consistency and leakage suppression strategies
3. 🧪 抵抗および容量パラメータの参照
Reference for Resistance and Capacitance Parameters
下記は、代表的な文献および業界標準値に基づいています：
The following are based on representative literature values and industry-standard references:
- 拡散・ポリ・金属の $R_{\text{sheet}}$ は、0.18μm CMOS世代の典型値を参照
→ Sheet resistance ($R_{\text{sheet}}$) of diffusion, poly, and metal layers refers to typical values for 0.18μm CMOS - Kelvin法によるコンタクト抵抗や、ベンダー提供のモデル値をベースに算出
→ Contact resistances are based on Kelvin measurements and vendor models - 配線層の抵抗は、CMP・温度依存性・配線幅などを加味して範囲化
→ Metal layer resistances are range-estimated considering CMP effects, temperature dependence, and wire width
⚠️ 注意 / Disclaimer：
本ドキュメントの数値は、あくまで教育・設計演習を目的とした「代表的な推定値」であり、ファウンドリやPDKにより異なる場合があります。
The values presented are intended as representative estimations for educational and design training purposes. Actual values may vary by foundry or PDK.
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