🧪 0.18μm CMOS Logic Process Flow (with Co Salicide & Metal-3)

⚠️ Caution

⚠️ Caution: This process flow is a memory-based reference model
The 0.18μm CMOS logic process flow presented here has been reconstructed based on the author’s past experience and recollection.
The sequence, processing conditions, and dimensions may not fully reflect actual manufacturing specifications, and accuracy is not guaranteed.
Please use this content with appropriate discretion and technical judgment.



📋 Process Table

Step Name Process Description Category Purpose Condition CD Thickness Mask
FS-DP SiON protection film deposition General Interface protection 200Å @ 700℃ - - -
FSN-DP Oxidation barrier nitride for STI Field Field oxidation cap 1500Å @ 750℃ - - -
F-PH Photolithography (mask exposure) Field STI pattern definition - 0.28μm - F
F-ET Etching (RIE etc.) Field STI pattern transfer - 0.28μm - -
F-DP STI oxide trench fill Field Shallow trench fill - - 4000Å -
F-CMP STI CMP planarization Field Planarization - - - -
PRE-OX Sacrificial oxide formation Pre-treatment Surface conditioning and contamination capture before implantation Dry OX, ~80Å - 80Å -
NWL-PH Photolithography (Mask Exposure) Well Patterning of N-Well region - - - NWL
NWL-ION Ion Implantation Well Formation of N-Well 800 keV, 2E13 cm⁻² - - -
PWL-PH Photolithography (Mask Exposure) Well Patterning of P-Well region - - - PWL
PWL-ION Ion Implantation Well Formation of P-Well 200 keV, 5E12 cm⁻² - - -
NCD-PH Photolithography (Mask Exposure) CD Patterning of NMOS channel region - - - NCD
NCD-ION Ion Implantation (Channel Doping) CD Threshold voltage adjustment for NMOS Boron, 50 keV, 1E13 cm⁻² - - -
PCD-PH Photolithography (Mask Exposure) CD Patterning of PMOS channel region - - - PCD
PCD-ION Ion Implantation (Channel Doping) CD Threshold voltage adjustment for PMOS BF₂, 30 keV, 1E13 cm⁻² - - -
G-OX Gate oxide formation Gate Channel oxide (EOT control) Dry OX, EOT=35Å - 35Å -
PLY-DP Poly-Si gate deposition Gate Gate electrode formation LPCVD - 1500Å -
PLY-PH Photolithography Gate Poly gate resist patterning KrF 0.18μm - PLY
PLY-ET Poly gate etching Gate Gate structure definition RIE 0.18μm - -
NLD-PH Photolithography S/D NMOS LDD mask KrF 0.18μm - NLD
NLD-ION Ion implantation S/D NMOS LDD doping As, 30keV, 1E13 - - -
PLD-PH Photolithography S/D PMOS LDD mask KrF 0.18μm - PLD
PLD-ION Ion implantation S/D PMOS LDD doping BF₂, 30keV, 1E13 - - -
SW-DP Spacer deposition (SiN) Gate LDD spacer LPCVD - 800Å -
SW-ET Spacer etching Gate Spacer patterning RIE - - -
NLD2-PH Photolithography S/D NMOS 2nd LDD mask KrF 0.22μm - NLD2
NLD2-ION Ion implantation S/D NMOS deep S/D extension As, 40keV, 1E13 - - -
PLD2-PH Photolithography S/D PMOS 2nd LDD mask KrF 0.22μm - PLD2
PLD2-ION Ion implantation S/D PMOS deep S/D extension BF₂, 40keV, 1E13 - - -
CO-SP Co sputtering Salicide Precursor deposition - - 300Å -
LMP-ANL Salicide anneal Salicide CoSi formation 550℃, 30s - - -
CO-ET Selective Co etch Salicide Residual removal H₂SO₄-based - - -
LMP2-ANL Phase transformation anneal Salicide CoSi₂ formation 750℃, 30s - - -
F2-DP ILD deposition ILD Inter-metal insulation PE-TEOS - 6000Å -
F2-CMP ILD CMP CMP Planarization CMP - - -
CNT-PH Photolithography Via Via-1 patterning - 0.24μm - CNT
CNT-ET Etching Via Via-1 transfer - 0.24μm - -
TIN-SP Ti/TiN barrier deposition Via Barrier formation 300Å - 300Å -
CW-DP W plug fill Plug Via-1 fill - - 5000Å -
CW-CMP W CMP Plug Planarization CMP - - -
ALA-SP Al deposition (Metal-1) Interconnect Local routing - - 6000Å -
ALA-PH Photolithography Interconnect Metal-1 pattern - 0.28μm - ALA
ALA-ET Etching Interconnect Metal-1 transfer - 0.28μm - -
HLA-DP ILD-1 deposition ILD Above Metal-1 PE-TEOS - 6000Å -
HLA-PH Photolithography ILD Via-2 patterning RIE + litho 0.24μm - HLA
HLA-ET Etching ILD Via-2 transfer RIE + litho 0.24μm - -
TINA-SP Ti/TiN barrier Barrier Via-2 barrier 300Å - 300Å -
HWA-DP W plug fill (Via-2) Plug Metal-2 contact W-CVD - 5000Å -
HWA-CMP W CMP (Via-2) Plug Planarization CMP - - -
ALB-SP Al deposition (Metal-2) Interconnect Intermediate metal - - 6000Å -
ALB-PH Photolithography Interconnect Metal-2 pattern - 0.35μm - ALB
ALB-ET Etching Interconnect Metal-2 transfer - 0.35μm - -
HLB-DP ILD-2 deposition ILD Above Metal-2 PE-TEOS - 6000Å -
HLB-PH Photolithography ILD Via-3 patterning RIE + litho 0.28μm - HLB
HLB-ET Etching ILD Via-3 transfer RIE + litho 0.28μm - -
TINB-SP Ti/TiN barrier Barrier Via-3 barrier 300Å - 300Å -
HWB-DP W plug fill (Via-3) Plug Metal-3 contact W-CVD - 5000Å -
HWB-CMP W CMP (Via-3) Plug Planarization CMP - - -
ALC-SP Al deposition (Metal-3) Interconnect Global routing - - 8000Å -
ALC-PH Photolithography Interconnect Metal-3 pattern - 0.5μm - ALC
ALC-ET Etching Interconnect Metal-3 transfer - 0.5μm - -
HLC-DP ILD-3 deposition ILD Above Metal-3 PE-TEOS - 6000Å -
HLC-PH Photolithography ILD Pad via patterning RIE + litho 0.35μm - HLC
HLC-ET Etching ILD Pad via transfer RIE + litho 0.35μm - -
TINC-SP Ti/TiN barrier Barrier Pad via barrier 300Å - 300Å -
HWC-DP W plug fill (Pad via) Plug Pad contact W-CVD - 5000Å -
HWC-CMP W CMP (Pad via) Plug Planarization CMP - - -
ALD-SP Al deposition (Pad) Pad Bond pad formation - - 10000Å -
ALD-PH Photolithography Pad Pad pattern - 3.0μm - PAD
ALD-ET Etching Pad Pad transfer - 3.0μm - -
PAD-DP Passivation deposition Protection Surface/environmental protection SiN+SiO₂ - 8000Å -
PAD-PH Photolithography Protection Opening pattern - 3.0μm - PAD
PAD-ET Etching Protection Final pad opening - 3.0μm - -
AL-SNT Hydrogen sintering Surface treatment Al oxide reduction / interface stabilization H₂/N₂, 420℃, 30min - - -
E-TEST Electrical test Test Vth, Ioff measurement Automatic tester - - -

📸 0.18μm CMOS Photolithography Exposure Map (English Version)

This document summarizes the photolithography conditions (equipment, reduction ratio, wavelength) for each mask layer in a 0.18μm CMOS logic process.
It helps clarify the relationship between design rules and lithography capabilities, including stepper selection (e.g., Nikon 5:1, Canon 2:1).

📋 Exposure Condition Table

Step Name Target Layer CD Target Equipment Reduction Ratio Wavelength Notes
F-PH STI Isolation 0.28μm Nikon NSR-S204B 5:1 KrF (248nm) High-resolution required
NWL-PH N-Well >0.6μm Canon FPA-3000i5+ 2:1 i-line (365nm) CD resolution not critical
PWL-PH P-Well >0.6μm Canon FPA-3000i5+ 2:1 i-line (365nm) Same as above
NCD/PCD-PH Channel Doping ~0.6μm Canon FPA-3000i5+ 2:1 i-line (365nm) Electrical performance focus
PLY-PH Poly Gate 0.18μm Nikon NSR-S306C 5:1 KrF (248nm) Critical CD layer
NLD/PLD-PH LDD (shallow) 0.18μm Nikon NSR-S306C 5:1 KrF (248nm) Precise doping
NLD2/PLD2-PH LDD (deep) 0.22μm Canon FPA-3000i5+ 2:1 i-line (365nm) Sufficient with i-line
CNT-PH Contact 0.24μm Nikon NSR-S204B 5:1 KrF (248nm) Critical contact opening
ALA-PH Metal-1 0.28μm Nikon NSR-S204B 5:1 KrF (248nm) Cell-level interconnect
HLA-PH Via-1 0.24μm Nikon NSR-S204B 5:1 KrF (248nm) High via accuracy
ALB-PH Metal-2 0.35μm Canon FPA-3000i5+ 2:1 i-line (365nm) Intermediate metal
HLB-PH Via-2 0.28μm Canon FPA-3000i5+ 2:1 i-line (365nm) Via layer
ALC-PH Metal-3 0.5μm Canon FPA-3000i5+ 2:1 g-line (436nm) Global interconnect
HLC-PH Via-3 0.35μm Canon FPA-3000i5+ 2:1 i-line (365nm) Large via
ALD-PH Pad Metal 3.0μm Canon FPA-3000i5+ 2:1 g-line (436nm) Bonding pad
PAD-PH Passivation 3.0μm Canon FPA-3000i5+ 2:1 g-line (436nm) Final opening

🔍 Notes


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