🎛️ EduController: Educational Framework for Control Theory and AI Control
🔗 Official Links
Language | GitHub Pages 🌐 | GitHub 💻 |
---|---|---|
🇺🇸 English | ||
🇯🇵 Japanese |
📘 Overview
EN:
EduController is a step-by-step, practical educational project that covers classical control, modern control, and AI-based next-generation control. It supports a wide range of topics from intuitive understanding of control theory in Python to HDL coding and LLM-integrated design.
🌐 Toward Next-Generation Control — FSM × PID × LLM
A three-layer hybrid control architecture with AITL Framework
Integrating FSM, PID, and LLM for intelligent control systems
🧭 Structure Overview
Track | Overview (EN) |
---|---|
🎛️ Control Theory Track (Part 01–05) | Classical control, state-space, digital control, practical implementation |
🤖 AI Control Track (Part 06–08) | Neural networks, reinforcement learning, data-driven control |
🧠 Integrated & Applied Control Track (Part 09–10) | LLM-integrated control, inverted pendulum control |
📚 Chapter Structure
🎛️ Control Theory Track / Classical & Modern Control
🤖 AI Control Track / AI-based Control
🧠 Integrated & Applied Control Track / Integrated Control
🔩 Implementation Toolkit
Directory | Summary |
---|---|
matlab_tools/ |
Visualization in Simulink, C code generation, HDL design. |
SoC_DesignKit_by_ChatGPT/ |
FSM, PID, LLM control templates, Verilog generation, testbench verification. |
🧭 Usage Flow Overview
These tools provide an end-to-end flow from model design to RTL verification.
Two types of C sources are supported (C generated from Simulink / handwritten C), enabling integration of PID/FSM/LLM control logic into HDL.
- Simulink or Handwritten C (matlab_tools/ etc.)
- Create a model in Simulink and generate fixed-point C code, or
prepare handwritten C step functions for FSM/LLM control.
- Create a model in Simulink and generate fixed-point C code, or
- C code → HDL (SoC_DesignKit_by_ChatGPT/)
- Map C functions (PID / FSM / LLM kernels, etc.) to templates,
and automatically generate Verilog/SystemVerilog plus testbenches. - Multiple C modules can be integrated within the same SoC (e.g., PID + FSM + LLM I/F).
- Map C functions (PID / FSM / LLM kernels, etc.) to templates,
- Simulation & Verification
- Verify functional equivalence between C implementation and RTL using the auto-generated testbench.
- Then proceed to synthesis and deployment in FPGA/ASIC flows as needed.
flowchart TB
A[Simulink Model]
A2[Handwritten C: FSM / LLM control]
B[C code - fixed-point]
C[SoC_DesignKit_by_ChatGPT Template Mapping]
D[RTL Generation : Verilog / SystemVerilog]
E[Testbench & Simulation]
F[FPGA / ASIC Synthesis]
A --> B
A2 --> B
B --> C
C --> D
D --> E
E --> F
🔗 Related Projects
👤 Author
📄 License
The default license is MIT, but the following specific directories/materials use a Hybrid License.
The default license is MIT, but specific directories/materials adopt a Hybrid License.
📌 Item | License | Description |
---|---|---|
Default | MIT License | Free to use, modify, and redistribute |
Hybrid Scope | Part05, Part09, Part10, matlab_tools, SoC_DesignKit_by_ChatGPT |
Depending on the nature of the materials, code, and diagrams, applies MIT License / CC BY 4.0 / CC BY-SA 4.0 / CC BY-NC 4.0 |
💬 Feedback
Propose improvements or start discussions via GitHub Discussions.